As known in the art, in many logic circuit applications, including those which are not controlled by a master timing clock ("asynchronous"), it is desirable to operate with three-state ("tri-state") capability. More specifically, it is desirable to have a number of separate buffer circuits each connecting a different one of a number of separate binary digital local input signal sources to a common data bus line. Each such buffer circuit has an output terminal connected to the common bus line, in order to deliver the corresponding digital local input signal to this common bus line if, and only if, no other signal is then actively present on that line from other sources, but otherwise to float (i.e., otherwise to present a very high impedance to the common data bus line).
For purpose of illustrating these concepts and with reference to FIG. 1, a binary digital "1" or "0" signal ("high" or "low" voltage) may or may not actively be present from other sources (not shown) on a common data bus line 11 at a given moment. By a signal "actively" present from other sources on the common data bus line is meant a low impedance driven signal from another source. In the absence of any such active signal from other sources, the common data bus line 11 is electrically "floating," that is to say, has a very high impedance to ground. Only if this common data bus line 11 is thus "floating," then a buffer circuit 20 is enabled by a control signal from the source 13 to allow passage of a local binary digital input signal 14 to an output terminal 12 on the bus line 11; but, if there is indeed a signal already actively present on the common data bus line 11, then the control signal source 13 prevents the buffer circuit 20 from passing any local signal 14 to the common data bus line 11 and causes this buffer circuit to present a very high impedance to the bus line, that is, the output of the buffer circuit 20 at terminal 12 is electrically in the "floating" state. This terminal 12 thus serves as a local signal output terminal of the buffer circuit 20. Since the local input signal 14 itself can be a "high" voltage (digital "1") or a "low" voltage (digital "0"), accordingly there are three possible local outputs or "states" ("1", "0", "float") of the buffer circuit 20 at its output terminal 12, depending upon the states of both the local signal input 14 and the control signal delivered by the source 13, all in accordance with the following:
______________________________________ Local Control Non-Inverting Signal Signal Buffer Circuit 14 13 Output ______________________________________ 0 1 float 1 1 float 0 0 0 1 0 1 ______________________________________
In the prior art, such a tri-state buffer circuit has been proposed in the form of an MOS integrated circuit, in N-MOS technology for example (FIG. 2). Basically such a circuit includes a pair of MOS NOR-gates (formed by transistors Q.sub.3, Q.sub.4, Q.sub.4 '; Q.sub.5, Q.sub.6, Q.sub.6 ') feeding an MOS output load device including an output "driver" transistor Q.sub.2 and an output load transistor Q.sub.1. It should be understood that each of the transistors Q.sub.4 and Q.sub.6 is a high transconductance transistor serving as a driver and is substantially identical to its corresponding parallel connected twin transistor Q.sub.4 ' and Q.sub.6 ', respectively. The transistors Q.sub.3 and Q.sub.5 are relatively low transconductance transistors serving as load elements. The gate electrode of each of the transistors Q.sub.3 and Q.sub.5 is connected to the drain terminal of the respective transistor when using such enhancement mode N-MOS devices. All transistors in the circuit shown in FIG. 2 are enhancement mode transistors, with the same threshold of typically about 1.2 volts. However, such a circuit requires both a relatively high voltage supply (V.sub.GG =+12 volt) in addition to a relatively low voltage supply (V.sub.DD =+5 volt) for reliable operation, because the existence of a non-vanishing threshold voltage of the output load transistor Q.sub.1 results in a "back-gate bias" of Q.sub.1 itself when it is in the "on" condition. This "back-gate bias" arises because the voltage at the source of Q.sub.1 becomes higher than the voltage of its substrate (ground), thereby increasing the required gate electrode voltage for turning this transistor "on", i.e., thereby increasing its threshold voltage during operation. This increase in threshold voltage during operation ("back-gate bias effect") prevents Q.sub.1 from being turned "on" properly unless the drains and gates of both the previous stages' NOR-gate load transistors (Q.sub.5, Q.sub.3) are connected to a relatively high voltage supply, typically +12 volt.
For example, when the output drive transistor Q.sub.2 is "off" and the output load transistor Q.sub.1 is "on," then the potential of the output terminal 12 tends toward V.sub.DD, thereby undesirably tending to shut "off" this output load transistor Q.sub.1 by virtue of the back-gate bias effect on its threshold, unless the voltage being applied to its gate electrode be increased above V.sub.DD by a higher drain voltage supply (V.sub.GG =12 volts) to Q.sub.5. For example, if the threshold of Q.sub.1 is 1.2 volts under the condition of zero "back-gate bias," i.e., when the source of Q.sub.1 is at the same ("ground") potential as that of the semiconductor substrate, then this threshold will rise to as much as about 3 volts when the source of Q.sub.1 is at a potential of 4 or 5 volts, i.e., when Q.sub.1 itself is "on"; accordingly, since the load transistor Q.sub.5, which is then also "on", suffers from this same type of back-gate bias threshold effect, therefore the source potential of Q.sub.5 will not rise to the required voltage of about 3 volts necessary to keep Q.sub.1 "on" unless the drain of Q.sub.5 be supplied considerably more than 5 volts or unless Q.sub.5 be a depletion mode N-MOS transistor with its gate electrode connected to its source. But even if Q.sub.5 is such a depletion mode device, thereby supplying 5 volts to the gate of Q.sub.1 ; nevertheless, when Q.sub.1 is "on," the source of the output load transistor Q.sub.1 will not be able to rise to much above 2 (=5-3) volts, instead of a desired 3 or more volts, unless the supply to the drain of this output load transistor Q.sub.1 and to the drain (and gate) of Q.sub.5 be raised, to say 12 volts. The use of such a high voltage drain supply requires the use of an additional voltage supply (i.e., +12 volts as well as +5 volts), and also results in the problem of undesirably large amounts of power being drawn during operation. Accordingly, it would be desirable to have a tri-state MOS buffer circuit which does not suffer from this problem.